The present invention relates generally to timing convergence, and more particularly to estimating timing convergence using assertion comparisons.
The structure and behavior of electronic circuits and digital logic circuits can be described using a hardware description language (HDL). HDLs enable precise, formal descriptions of electronic circuits that allow for automated analysis and simulation. For example, the electronic circuits may include complex circuits such as application-specific integrated circuits (ASICs), microprocessors, and programmable logic devices (PLDs). HDLs may be used to express the structure of electronic systems and their behavior over time. HDLs thus also include an explicit notion of time, which may be a primary attribute of hardware. For example, the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is an HDL used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. A macro written in VHDL may include multiple design abstractions organized as a hierarchy. Macros may be also referred herein as cells or blocks. In some examples, a macro can be a synthesizable register-transfer level (RTL) or manually designed. For example, a macro may be any cell that can be placed and routed in a placement and routing tool. A macro can be editable and can contain standard cells or any other sub macros. In some examples, a macro can be optimized for power, area, or timing. In some examples, the inputs for a macro can include feedback assertions, size of the macro, RTL, clock placement, among other inputs. For example, a higher level of a hierarchy may be a register-transfer level (RTL). An RTL can be used to model a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. In some examples, lower-level representations and ultimately actual wiring can be derived from higher level representations.
Feedback assertions can be included in synthesized macros in order to analyze timing in the macros. During a project lifetime, the values of feedback assertions given to synthesizable blocks may tend to change and thus be unstable. This instability may be particularly prevalent in early stages of project development until timing converges. As used herein, convergence refers to a state wherein timing feedback assertions of a macro may fluctuate within a window or threshold difference of time. Moreover, instability at higher levels of a design hierarchy may result in even greater instability at lower levels of the hierarchy. For example, fluctuations of timing at the flow of a digital signal level may translate to even greater fluctuations at the lower-level representations due to additional delays caused by wiring, etc. Thus, the timing of higher level representations is generally stabilized before additional parameters of a project, such as power, size, space, etc., can then be analyzed and modified accordingly. However, it is difficult to determine how close to timing convergence a project may be by looking at the values of feedback assertions. Thus, efficiently scheduling tasks that depend on convergence may also be very difficult.